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16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 1 16mb: x16 it sdram key timing parameters speed clock access time setup hold cl = 3** -6 166 mhz 5.5ns 2ns 1ns -7 143 mhz 5.5ns 2ns 1ns -8a 125 mhz 6ns 2ns 1ns *off-center parting line **cl = cas (read) latency 1 meg x 16 configuration 512k x 16 x 2 banks refresh count 2k or 4k row addressing 2k (a0-a10) bank addressing 2 (ba) column addressing 256 (a0-a7) synchronous dram MT48LC1M16A1 sit - 512k x 16 x 2 banks industrial temperature for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/sdr amds. html pin assignment (top view) 50-pin tsop features ? pc100 functionality fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge 1 meg x 16 - 512k x 16 x 2 banks architecture with 11 row, 8 column addresses per bank programmable burst lengths: 1, 2, 4, 8 or full page auto precharge mode, includes concurrent auto precharge self refresh and adaptable auto refresh modes - 32ms, 2,048-cycle refresh or - 64ms, 2,048-cycle refresh or - 64ms, 4,096-cycle refresh lvttl-compatible inputs and outputs single +3.3v 0.3v power supply supports cas latency of 1, 2 and 3 industrial temperature range: -40c to +85c options marking configuration 1 meg x 16 (512k x 16 x 2 banks) 1m16a1 plastic package - ocpl* 50-pin tsop (400 mil) tg timing (cycle time) 6ns (166 mhz) -6 7ns (143 mhz) -7 8ns (125 mhz) -8a refresh 2k or 4k with self refresh mode at 64ms s operating temperature -40c to +85c it part number example: MT48LC1M16A1tg-7sit note: the # symbol indicates signal is active low. v dd dq0 dq1 vssq dq2 dq3 v dd q dq4 dq5 vssq dq6 dq7 v dd q dqml we# cas# ras# cs# ba a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 vss dq15 dq14 vssq dq13 dq12 v dd q dq11 dq10 vssq dq9 dq8 v dd q nc dqmh clk cke nc a9 a8 a7 a6 a5 a4 vss 16mb (x16) sdram part number part number architecture MT48LC1M16A1tg sit 1 meg x 16
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 2 16mb: x16 it sdram precharge that is initiated at the end of the burst sequence. the 1 meg x 16 sdram uses an internal pipelined architecture to achieve high-speed operation. this archi- tecture is compatible with the 2 n rule of prefetch architec- tures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing the alter- nate bank will hide the precharge cycles and provide seamless, high-speed, random-access operation. the 1 meg x 16 sdram is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdrams offer substantial advances in dram operat- ing performance, including the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between inter- nal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. general description the 16mb sdram is a high-speed cmos, dynamic random-access memory containing 16,777,216 bits. it is internally configured as a dual 512k x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 512k x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba selects the bank, a0-a10 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 3 16mb: x16 it sdram table of contents functional block diagram - 1 meg x 16 ................. 3 pin descriptions ........................................................ 4 functional description ........................................ 5 initialization ........................................................ 5 register definitions ............................................. 5 mode register ................................................ 5 burst length .............................................. 5 burst type ................................................. 5 cas latency .............................................. 7 operating mode ....................................... 7 write burst mode ..................................... 7 commands .............................................................. 8 truth table 1 (commands and dqm operation) .............. 8 command inhibit ............................................... 9 no operation (nop) .......................................... 9 load mode register ............................................ 9 active .................................................................. 9 read .................................................................. 9 write .................................................................. 9 precharge ............................................................. 9 auto precharge .................................................... 9 burst terminate ................................................... 9 auto refresh ........................................................ 10 self refresh .......................................................... 10 operation ................................................................ 11 bank/row activation ......................................... 11 reads .................................................................. 12 writes .................................................................. 18 precharge ............................................................. 20 power-down ....................................................... 20 clock suspend .................................................... 21 burst read/single write ...................................... 21 concurrent auto precharge ................................ 22 truth table 2 (cke) ................................................... 24 truth table 3 (current state, same bank) ....................... 25 truth table 4 (current state, different bank) ................... 27 absolute maximum ratings .................................... 29 dc electrical characteristics and operating conditions ........................................... 29 i dd specifications and conditions .......................... 29 capacitance .............................................................. 30 ac electrical characteristics (timing table) .... 30 timing waveforms initialize and load mode register ...................... 33 power-down mode ............................................ 34 clock suspend mode .......................................... 35 auto refresh mode ............................................. 36 self refresh mode ............................................... 37 reads read - single read ......................................... 38 read - without auto precharge .................... 39 read - with auto precharge .......................... 40 alternating bank read accesses .................... 41 read - full-page burst .................................... 42 read - dqm operation ................................. 43 writes write - single write ....................................... 44 write - without auto precharge ................... 45 write - with auto precharge ......................... 46 alternating bank write accesses ................... 47 write - full-page burst ................................... 48 write - dqm operation ................................ 49
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 4 16mb: x16 it sdram 11 11 11 ras# refresh controller 2,048 refresh counter cas# 256 256 (x16) 8 column- address buffer burst counter row- address mux clk cs# we# cke 256 (x16) bank1 memory array (2,048 x 256 x 16) sense amplifiers i/o gating dqm mask logic control logic column decoder column- address latch 8 mode register row- address latch 11 row decoder 11 command decode dq0- dq15 a0-a10, ba 16 8 dqml, dqmh 256 2,048 bank0 memory array (2,048 x 256 x 16) row decoder row- address latch 11 12 address register 12 sense amplifiers i/o gating dqm mask logic data input register data output register 16 16 functional block diagram 1 meg x 16 sdram
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 5 16mb: x16 it sdram pin descriptions pin numbers symbol type description 35 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 34 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operations (all banks idle), active power-down (row active in either bank) or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power- down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. 18 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 15, 16, 17 w e#, cas#, input command inputs: ras#, cas# and we# (along with cs#) define the ras# com mand being entered. 14, 36 dqml, input input/output mask: dqm is an input mask signal for write accesses and an dqmh output enable signal for read accesses. input data is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqm is sampled high during a read cycle. dqml corresponds to dq0-dq7; dqmh corresponds to dq8-dq15. dqml and dqmh are considered same state when referenced as dqm. 19 ba input bank address inputs: ba defines to which bank the active, read, write or precharge command is being applied. ba is also used to program the twelfth bit of the mode register. 21-24, 27-32, 20 a0-a10 input address inputs: a0-a10 are sampled during the active command (row-address a0-a10) and read/write command (column-address a0- a7, with a10 defining auto precharge) to select one location out of the 512k available in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high). the address inputs also provide the op-code during a load mode register command. 2, 3, 5, 6, 8, 9, dq0- input/ data i/os: data bus. 11, 12, 39, 40, 42, dq15 output 43, 45, 46, 48, 49 33, 37 nc ? no connect: these pins should be left unconnected. 7, 13, 38, 44 v dd q supply dq pow er: provide isolated power to dqs for improved noise immu- nity. 4, 10, 41, 47 v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. 1, 25 v dd supply power supply: +3.3v 0.3v. 26, 50 v ss supply ground.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 6 16mb: x16 it sdram functional description in general, the sdram is a dual 512k x 16 dram that operates at 3.3v and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 512k x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba selects the bank, a0-a10 select the row). the address bits (a0-a7) registered coincident with the read or write command are used to select the starting col- umn location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register defi- nition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to v dd and v dd q (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to applying any command other than a com- mand inhibit or a nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied, with at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 1. the mode register is programmed via the load mode register com- mand and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 1. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full- page burst is available for the sequential type. the full- page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown op- eration or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 when the burst length is set to two, by a2-a7 when the burst length is set to four and by a3- a7 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the starting column address, as shown in table 1.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 7 16mb: x16 it sdram note: 1. for a burst length of two, a1-a7 select the block of two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2-a7 select the block of four burst; a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a7 select the block of eight burst; a0-a2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0-a7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0-a7 select the unique column to be accessed, and mode register bit m3 is ignored. table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a7 cn, cn+1, cn+2 page cn+3, cn+4... not supported (256) (location 0-255) ? cn-1, cn ? figure 1 mode register definition 000 001 010 011 100 101 110 111 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleave cas latency reserved 1 2 3 reserved reserved reserved reserved 000 001 010 011 100 101 110 111 burst length m0 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 m2 m3 m4 m5 m6 m6 - m0 m8 m7 op mode a10 ba 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 8 16mb: x16 it sdram will be valid by t2, as shown in figure 2. table 2 below indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used, as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. table 2 cas latency cas latency the cas latency is the delay, in clock cycles, be- tween the registration of a read command and the availability of the first piece of output data. the la- tency can be set to 1, 2 or 3 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0, and the latency is programmed to two clocks, the dqs will start driving after t1 and the data allowable operating frequency (mhz) cas cas cas speed latency = 1 latency = 2 latency = 3 -6 50 125 166 -7 40 100 143 -8a 40 77 125 figure 2 cas latency clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don ? t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 9 16mb: x16 it sdram truth table 1 ? commands and dqm operation (notes: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column and l h l l l/h 8 bank/col valid 4 start write burst) burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x o p-code x 2 write enable/output enable ???? l ? active 8 write inhibit/output high-z ???? h ? high-z 8 following the operation section; these tables provide current state/next state information. commands truth table 1 provides a quick reference of available commands. this is followed by a written description of each command. three additional truth tables appear note: 1. cke is high for all commands shown except self refresh. 2. a0-a10 and ba define the op-code written to the mode register. 3. a0-a10 provide row address, and ba determines which bank is made active. 4. a0-a7 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba determines which bank is being read from or written to. 5. for a10 low, ba determines which bank is being precharged; for a10 high, all banks are precharged and ba is a ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 10 16mb: x16 it sdram command inhibit the command inhibit function prevents new commands from being executed by the sdram, re- gardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-a10 and ba. see mode register heading in register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba input selects the bank, and the address provided on inputs a0-a10 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge com- mand must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba input selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs, subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba input selects the bank, and the address provided on inputs a0-a7 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input ba selects the bank. otherwise ba is treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write com- mands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is auto- matically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write com- mand. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 11 16mb: x16 it sdram burst terminate the burst terminate command is used to trun- cate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated as shown in the operation section of this data sheet. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before- ras# (cbr) refresh in conventional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing during an auto refresh com- mand is generated by an internal refresh controller. this means that the address lines are not used to generate the refresh address, and are ?don?t care?. the 1 meg x 16 sdram requires 2,048 auto refresh cycles every 64ms ( t ref) to ensure that each row is refreshed. distributed refresh would be achieved by providing an auto refresh command once ev- ery 31.25s. burst refresh could be accomplished by issuing 2,048 auto refresh commands consecu- tively at the minimum cycle rate of t rc. to provide a 4k refresh scheme, the refresh rate would be doubled. thus, 2,048 auto-refresh com- mands distributed every 15.625s would allow the 1 meg x 16 sdram to have a 4k refresh if required. of the three types of refreshs options, utilizing the 2,048 cycles every 64ms (31.25s per refresh) provides the maximum power savings. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care,? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to per- form its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras, and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defined as a signal cycling within timing con- straints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr, because time is required for the completion of any internal refresh in progress. upon exiting self refresh mode, auto refresh commands may be issued every 15.625s or less as both self refresh and auto refresh utilize the row refresh counter.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 12 16mb: x16 it sdram operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the ac- tive command, which selects both the bank and the row to be activated (see figure 3). after opening a row (issuing an active com- mand) a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be issued. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks rounded to 3. this is reflected in figure 4, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. the minimum time interval between successive active com- mands to different banks is defined by t rrd. cs# we# cas# ras# cke clk a0-a10 ba row address high bank 0 bank 1 figure 3 activating a specific row in a specific bank figure 4 example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd don ? t care
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 13 16mb: x16 it sdram upon completion of a burst, assuming no other commands have been initiated, the dqs will go high- z. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). data from any read burst may be truncated with a subsequent read command, and data from a fixed- length read burst may be immediately followed by data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst which is being trun- cated. the new read command should be issued x cycles before the clock edge at which the last desired reads read bursts are initiated with a read command, as shown in figure 5. the starting column and bank addresses are pro- vided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 6 shows general timing for each possible cas latency setting. figure 5 read command figure 6 cas latency cs# we# cas# ras# cke clk column address a0-a7 a10 ba bank 0 bank 1 high enable auto precharge disable auto precharge a8-a9 clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don ? t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 14 16mb: x16 it sdram data element is valid, where x equals the cas latency minus one. this is shown in figure 7 for read latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 1 meg x 16 sdram uses a pipelined architec- figure 7 consecutive read bursts ture and therefore does not require the 2 n rule associ- ated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed, random read accesses within a page can be performed as shown in figure 8. clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n don ? t care nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles note: each read command may be to either bank. dqm is low. cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 15 16mb: x16 it sdram figure 8 random read accesses clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don ? t care d out n d out a d out x d out m read note: each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 16 16mb: x16 it sdram data from any read burst may be truncated with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a subsequent write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be the possibility that the device driving the input data would go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention as shown in figures 9 and 10. the dqm signal must be asserted (high) at least two clocks (dqm latency is two clocks for output buffers) prior to the write don ? t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. figure 10 read to write with extra clock cycle figure 9 read to write read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a burst of one is used, then dqm is not required. command to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z) regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure 10, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted (dqm latency is zero clocks for input buffers) prior to the write command to ensure that the written data is not masked. figure 9 shows the case where the clock frequency allows for bus contention to be avoided without add- ing a nop cycle, and figure 10 shows the case where the additional nop is needed.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 17 16mb: x16 it sdram figure 11 read to precharge a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated) and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles be- fore the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 11 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a , col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a , row bank ( a or all) don ? t care x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) x = 2 cycles
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 18 16mb: x16 it sdram figure 12 terminating a read burst operation that would result from the same fixed- length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst termi- nate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 12 for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 don ? t care note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 19 16mb: x16 it sdram writes write bursts are initiated with a write com- mand, as shown in figure 13. the starting column and bank addresses are pro- vided with the write command and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the follow- ing illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write com- mand. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z, and any additional input data will be ignored (see figure 14). a full-page burst will continue until terminated. (at the end of the page it will wrap to column 0 and continue.) data for any write burst may be truncated with a subsequent write command, and data for a fixed- length write burst may be immediately followed by data for a subsequent write command. the new write command can be issued on any clock following the previous write command, and the data provided figure 15 write to write coincident with the new command applies to the new command. an example is shown in figure 15. data n + 1 is either the last of a burst of two, or the last desired of a longer burst. the 1 meg x 16 sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed, random write accesses within a page can be performed as shown in figure 16. clk dq d in n t2 t1 t3 t0 command address nop nop write d in n + 1 nop bank, col n note: burst length = 2. dqm is low. figure 14 write burst don ? t care clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b note: dqm is low. each write command may be to any bank. cs# we# cas# ras# cke clk column address a0-a7 a10 ba bank 0 bank 1 high enable auto precharge disable auto precharge a8-a9 figure 13 write command
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 20 16mb: x16 it sdram input data element is registered. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge com- mand. an example is shown in figure 18. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed- length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. data for any write burst may be truncated with a subsequent read command, and data for a fixed- length write burst may be immediately followed by a subsequent read command. once the read com- mand is registered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 17. data n + 1 is either the last of a burst of two, or the last desired of a longer burst. data for a fixed-length write burst may be fol- lowed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m note: each write command may be to any bank. dqm is low. figure 16 random write cycles figure 17 write to read clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 note: the write command may be to any bank, and the read command may be to any bank. dqm is low. cas latency = 2 for illustration. figure 18 write to precharge dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop din n din n + 1 active t rp don ? t care bank ( a or all) t wr note: dqm could remain low in this example if the write burst is a fixed length of two. future sdrams will require a t wr of at least two clocks. bank a , row dqm dq command address bank a , col n nop write precharge nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row nop t wr = 1 clk ( t ck t wr) t wr = 2 clk ( t ck < t wr)
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 21 16mb: x16 it sdram fixed-length or full-page write bursts can be trun- cated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 19, where data n is the last desired data element of a longer burst. figure 21 power-down figure 20 precharge command figure 19 terminating a write burst cs# we# cas# ras# cke clk a10 ba bank 1 high bank 0 and 1 bank 0 or 1 bank 0 a0-a9 t ras t rcd t rc all banks idle input buffers gated off exit power- down mode ( ) ( ) ( ) ( ) ( ) ( ) t cks < t cks command nop active enter power- down mode nop clk cke ( ) ( ) ( ) ( ) don ? t care clk dq din n (data) t2 t1 t0 command address burst terminate write next command bank, col n note: dqms are low (address) precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks (see figure 20). the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input ba selects the bank. when all banks are to be precharged, input ba is treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coincident with a nop or command inhibit, when no accesses are in progress (see figure 21). if power- down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buff- ers, excluding cke, for maximum power savings while in standby. the device may not remain in the power- down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 22 16mb: x16 it sdram dq command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 note: for this example, burst length = 4 or greater, and dqm is low. figure 22 clock suspend during write burst don ? t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 note: for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. cke internal clock nop figure 23 clock suspend during read burst clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is sus- pended. any command or data present on the input pins at the time of a suspended internal clock edge are ignored; any data present on the dq pins will remain driven; and burst counters are not incremented as long as the clock is suspended (see examples in figures 22 and 23). clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write com- mands result in the access of a single column location (burst of one) regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 23 16mb: x16 it sdram concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. micron sdrams support con- current auto precharge. four cases where concurrent auto precharge occurs are de- fined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 24). 2. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 25). clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop note: d q m is low. bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) figure 24 read with auto precharge interrupted by a read clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm note: 1. dqm is high at t2 to prevent d out - a +1 from contending with d in - d at t4. bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don ? t care figure 25 read with auto precharge interrupted by a write
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 24 16mb: x16 it sdram clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address note: 1. dqm is low. bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n figure 26 write with auto precharge interrupted by a read don ? t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop note: 1. dqm is low. bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m figure 27 write with auto precharge interrupted by a write write with auto precharge 3. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data- out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 4. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 27).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 25 16mb: x16 it sdram truth table 2 ? cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l power-down x m aintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend l h power-down command inhibit or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibit or nop power-down entry all banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see truth table 3 note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1 .
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 26 16mb: x16 it sdram truth table 3 ? current state bank n - command to bank n (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) l l h h active (select and activate row) idle l l l h auto refresh 7 llll load mode register 7 l l h l precharge 11 l h l h read (select column and start read burst) 10 row active l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read l h l h read (select column and start new read burst) 10 (auto l h l l write (select column and start write burst) 10 precharge l l h l precharge (truncate read burst, start precharge) 8 disabled) l h h l burst terminate 9 write l h l h read (select column and start read burst) 10 (auto l h l l w rite (select column and start new write burst) 10 precharge l l h l precharge (truncate write burst, start precharge) 8 disabled) l h h l burst terminate 9 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged and t rp has been met. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a wr ite burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank, should be issued on any clock edge occuring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: sta rts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 27 16mb: x16 it sdram note (continued): 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 28 16mb: x16 it sdram truth table 4 ? current state bank n - command to bank m (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row activating, l l h h active (select and activate row) active or l h l h read (select column and start read burst) 7 precharging l h l l write (select column and start write burst) 7 l l h l precharge read l l h h active (select and activate row) (auto l h l h read (select column and start new read burst) 7, 10 precharge l h l l write (select column and start write burst) 7, 11 disabled) l l h l precharge 9 write l l h h active (select and activate row) (auto l h l h read (select column and start read burst) 7, 12 precharge l h l l w rite (select column and start new write burst) 7, 13 disabled) l l h l precharge 9 read l l h h active (select and activate row) (with auto l h l h read (select column and start new read burst) 7, 8, 14 precharge) l h l l write (select column and start write burst) 7, 8, 15 l l h l precharge 9 write l l h h active (select and activate row) (with auto l h l h read (select column and start read burst) 7, 8, 16 precharge) l h l l w rite (select column and start new write burst) 7, 8, 17 l l h l precharge 9 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged and t rp has been met. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a wr ite burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: sta rts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 29 16mb: x16 it sdram note (continued): 4. auto refresh, self refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been inter- rupted by bank m ? s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later (figure 7). 11. for a read without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figures 9 and 10). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (figure 17), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 13. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered (figure 15). the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 24). 15. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 25). 16. for a write with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 17. for a write with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock prior to the write to bank m (figure 27).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 30 16mb: x16 it sdram dc electrical characteristics and operating conditions (notes: 1, 6) (-40 c t a +85 c; v dd , v dd q = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd , v dd q 3 3.6 v input high voltage: logic 1; all inputs v ih 2.2 v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd i i -5 5 a (all other pins not under test = 0v) output leakage current: dqs are disabled; 0v v out v dd qi oz -10 10 a output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ? 0.4 v i dd specifications and conditions (notes: 1, 6, 11, 13) (-40 c t a +85 c; v dd , v dd q = +3.3v 0.3v) parameter/condition symbol -6 -7 -8a units notes operating current: active mode; i dd 1 145 140 135 ma 3, 18, burst = 2; read or write; t rc = t rc (min); 19, 26 cas latency = 3 standby current: power-down mode; i dd 2 222ma26 cke = low; all banks idle standby current: active mode; cs# = high; i dd 3 45 40 35 ma 3, 12, cke = high; all banks active after t rcd met; 19, 26 no accesses in progress operating current: burst mode; continuous burst; i dd 4 140 130 100 ma 3, 18, read or write; all banks active, cas latency = 3 19, 26 auto refresh current: t rc = 15.625s; cas latency = 3; i dd 5 45 40 35 ma 3, 12, cs# = high; cke = high 18, 19, 26 self refresh current: cke 0.2v i dd 6 111ma4 absolute maximum ratings* voltage on v dd , v dd q supply relative to v ss ................................ -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ................................ -1v to +4.6v operating temperature, t a (ambient) -40c to +85c storage temperature (plastic) .......... -55c to +150c power dissipation .................................................. 1w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. max
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 31 16mb: x16 it sdram electrical characteristics and recommended ac operating conditions (notes: 5, 6, 8, 9, 11) (-40 c t a +85 c) ac characteristics -6 -7 -8a parameter symbol min max min max min max units notes access time from clk (pos. edge) cl = 3 t ac 5.5 5.5 6 ns cl = 2 t ac 8 8.5 9 ns 22 cl = 1 t ac 18 22 22 ns 22 address hold time t ah 1 1 1 ns address setup time t as 2 2 2 ns clk high level width t ch 2.5 2.75 3 ns clk low level width t cl 2.5 2.75 3 ns clock cycle time cl = 3 t ck 6 7 8 ns 23 cl = 2 t ck 8 10 13 ns 22, 23 cl = 1 t ck 20 25 25 ns 23 cke hold time t ckh 1 1 1 ns cke setup time t cks 2 2 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 2 2 2 ns data-in hold time t dh 1 1 1 ns data-in setup time t ds 2 2 2 ns data-out high-impedance time cl = 3 t hz 5.5 5.5 6 ns 10 cl = 2 t hz 6 8.5 9 ns 10 cl = 1 t hz 18 22 22 ns 10 data-out low-impedance time t lz 1 1 1 ns data-out hold time t oh 1.5 1.5 1.5 ns active to precharge command t ras 42 120,000 42 120,000 48 120,000 ns auto refresh, active command period t rc 60 70 80 ns 22 auto refresh period t rcar 66 70 80 ns active to read or write delay t rcd 18 20 24 ns 22 refresh period - 2,048 or 4,096 rows t ref 64 64 64 ms precharge command period t rp 18 21 24 ns 22 active bank a to active bank b command t rrd 12 14 16 ns transition time t t 0.3 1.2 0.3 1.2 0.3 10 ns 7 write recovery time t wr 1 + 4ns 1 + 3ns 1 + 2ns t ck 24 10 10 10 ns 25 exit self refresh to active command t xsr 80 80 80 ns 20 capacitance parameter symbol min max units notes input capacitance: clk c i 1 2.5 4.0 p f 2 input capacitance: all other input-only pins c i 2 2.5 5.0 p f 2 input/output capacitance: dqs c io 4.0 6.5 p f 2
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 32 16mb: x16 it sdram ac functional characteristics (notes: 5, 6, 7, 8, 9, 11) (-40 c t a +85 c) parameter symbol -6 -7 -8a units notes read/write command to read/write command t ccd 1 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd000 t ck 17 dqm to data mask during writes t dqm 0 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 2 t ck 17 write command to input data delay t dwd 0 0 0 t ck 17 data-in to active command cl = 3 t dal 5 5 5 t ck 15, 21 cl = 2 t dal 4 4 4 t ck 15, 21 cl = 1 t dal 3 3 3 t ck 15, 21 data-in to precharge t dpl 2 2 2 t ck 16 last data-in to burst stop command t bdl000 t ck 17 last data-in to new read/write command t cdl111 t ck 17 last data-in to precharge command t rdl111 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 2 t ck 26 data-out to high-impedance from precharge command cl = 3 t roh 3 3 3 t ck 17 cl = 2 t roh 2 2 2 t ck 17 cl = 1 t roh 1 1 1 t ck 17
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 33 16mb: x16 it sdram 12.other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid v ih or v il levels. 13.i dd specifications are tested after the device is properly initialized. 14.timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15.timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16.timing actually specified by t wr. 17.required clocks are specified by jedec functional- ity and are not dependent on any timing param- eter. 18.the i dd current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19.address transitions average one transition every two-clock period. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 166 mhz for -6, 143 mhz for -7 and 125 mhz for -8a. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. the pulse width cannot be greater than one third of the cycle rate. 23.the clock frequency must remain constant during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24.auto precharge mode only. 25.precharge mode only. 26. t ck = 6ns for -6, 7ns for -7, 8ns for -8a. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40c t a +85c) is ensured. 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: q 30pf 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v with timing referenced to 1.5v crossover point.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 34 16mb: x16 it sdram initialize and load mode register t ch t cl t ck cke clk command dq address bank, row t rcar t mrd t rc auto refresh auto refresh program mode register. 2, 3 t cmh t cms precharge all banks. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) t cks power-up: v dd and clk stable. t=100s (min) t ah t as precharge nop nop auto refresh nop load mode register active nop nop nop code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) auto refresh bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don ? t care undefined ( ) ( ) ( ) ( ) t0 t1 tn + 1 to + 1 tp + 1 tp + 2 tp + 3 -6 -7 -8a symbol* min max min max min max units t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t mrd222 t ck t rc 60 70 80 n s t rcar 66 70 80 ns t rp 18 21 24 n s timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns *cas latency indicated in parentheses. note: 1. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. 2. the mode register may be loaded prior to the auto refresh cycles if desired. 3. outputs are guaranteed high-z after command is issued.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 35 16mb: x16 it sdram power-down mode 1 t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode. precharge all active banks. input buffers gated off while in power-down mode. exit power-down mode. ( ) ( ) ( ) ( ) don ? t care undefined t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle. address bank, row bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns note: 1. violating refresh requirements during power-down may result in loss of data. 2. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. -6 -7 -8a symbol* min max min max min max units *cas latency indicated in parentheses.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 36 16mb: x16 it sdram -6 -7 -8a symbol* min max min max min max units clock suspend mode 1 timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t hz (3) 5.5 5.5 6 ns t hz (2) 6 8.5 9 ns t hz (1) 18 22 22 ns t lz111ns t oh 1.5 1.5 1.5 ns t ch t cl t ck t ac t lz dqm 3 clk a0-a9 dq ba a10 t oh d out m t cms t ah t as t ah t as t ah t as bank t dh d in e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write don ? t care undefined cke t cks t ckh t cmh bank column m (a0 - a7) 2 column e (a0 - a7) 2 t ds d in e + 1 nop t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 *cas latency indicated in parentheses. note: 1. for this example, the burst length = 2, the cas latency = 3, and auto precharge is disabled. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 37 16mb: x16 it sdram auto refresh mode t ch t cl t ck cke clk dq t rcar ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank, row active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks. auto refresh t rc high-z address bank(s) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop dqm 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don ? t care undefined t0 t1 t2 tn + 1 to + 1 -6 -7 -8a symbol* min max min max min max units t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t rc 60 70 80 n s t rcar 66 70 80 ns t rp 18 21 24 n s timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns *cas latency indicated in parentheses. note: 1. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 38 16mb: x16 it sdram self refresh mode t ch t cl t ck t rp cke clk dq enter self refresh mode. precharge all active banks. t xsr clk stable prior to exiting self refresh mode. exit self refresh mode. (restart refresh time base.) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don ? t care undefined command t cmh t cms auto refresh precharge nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) address bank(s) ( ) ( ) ( ) ( ) high-z t cks ah as auto refresh > t ras ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqm 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t t cks t0 t1 t2 tn + 1 to + 1 to + 2 -6 -7 -8a symbol* min max min max min max units t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t ras 42 120,000 42 120,000 48 120,000 ns t rp 18 21 24 n s t xsr 80 80 80 n s timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns *cas latency indicated in parentheses. note: 1. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 39 16mb: x16 it sdram single read ? without auto precharge 1 timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t hz (3) 5.5 5.5 6 ns t hz (2) 6 8.5 9 ns t hz (1) 18 22 22 ns t lz111ns t oh 1.5 1.5 1.5 ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s *cas latency indicated in parentheses. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single banks don ? t care undefined column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqm / dqml, dqmh cke clk a0-a9, a11 dq ba0, ba1 a10 command -6 -7 -8a symbol* min max min max min max units note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ? manual ? precharge. 2. a8, a9 = ? don ? t care. ?
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 40 16mb: x16 it sdram read ? without auto precharge 1 bank 0 and 1 t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm 3 cke clk a0-a9 dq ba a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m +3 t ac t oh t ac t oh t ac d out m +2 d out m +1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge bank 0 or 1 don ? t care undefined column m (a0 - a7) 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t hz (3) 5.5 5.5 6 ns t hz (2) 6 8.5 9 ns t hz (1) 18 22 22 ns t lz111ns t oh 1.5 1.5 1.5 ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s *cas latency indicated in parentheses. -6 -7 -8a symbol* min max min max min max units note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ? manual ? precharge. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 41 16mb: x16 it sdram read ? with auto precharge 1 enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm 3 cke clk a0-a9 dq ba a10 t oh d out m t ah t as t ah t as t ah t as row column m (a0 - a7) 2 row bank bank row row bank don ? t care undefined t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms t cmh t cms nop nop nop active nop read nop active nop t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t hz (3) 5.5 5.5 6 ns t hz (2) 6 8.5 9 ns t hz (1) 18 22 22 ns t lz111ns t oh 1.5 1.5 1.5 ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s *cas latency indicated in parentheses. -6 -7 -8a symbol* min max min max min max units note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ? manual ? precharge. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 42 16mb: x16 it sdram enable auto precharge t ch t cl t ck t ac t lz dqm 3 clk a0-a9 dq ba a10 t oh d out m t cmh t cms t cmh t cms t ah t as t ah t as t ah t as row column m (a0 - a7) 2 row row row don ? t care undefined t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command nop nop active nop read nop active t oh d out b t ac t ac read column b (a0 - a7) 2 enable auto precharge row active row bank 0 bank 0 bank 1 bank 1 bank 0 cke t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 1 cas latency - bank 1 t t rc - bank 0 rrd alternating bank read accesses 1 timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh 1 1 1 ns t cms 2 2 2 ns t lz111ns t oh 1.5 1.5 1.5 ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 ns t rcd 18 20 24 ns t rp 18 21 24 ns t rrd 12 14 16 ns -6 -7 -8a symbol* min max min max min max units *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 43 16mb: x16 it sdram timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns read ? full-page burst 1 t ch t cl t ck t ac t lz t rcd cas latency dqm 3 cke clk a0-a9 dq ba a10 t oh d out m t cmh t cms t ckh t cks t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed. 256 locations within same row. don ? t care undefined command nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) column m (a0 - a7) 2 t ah t as bank ( ) ( ) ( ) ( ) bank ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 t3 t4 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 4 t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t hz (3) 5.5 5.5 6 ns t hz (2) 6 8.5 9 ns t hz (1) 18 22 22 ns t lz111ns t oh 1.5 1.5 1.5 ns t r c d 18 20 24 n s -6 -7 -8a symbol* min max min max min max units *cas latency indicated in parentheses. note: 1. for this example, the cas latency = 2. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. 4. page left open; no t rp.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 44 16mb: x16 it sdram read ? dqm operation 1 t ch t cl t ck t rcd cas latency dqm 3 cke clk a0-a9 dq ba a10 t cms row bank row bank don ? t care undefined t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh t cms t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t ah t as t ah t as column m (a0 - a7) 3 t ckh t cks enable auto precharge disable auto precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -6 -7 -8a symbol* min max min max min max units t ac (3) 5.5 5.5 6 ns t ac (2) 8 8.5 9 ns t ac (1) 18 22 22 ns t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t hz (3) 5.5 5.5 6 ns t hz (2) 6 8.5 9 ns t hz (1) 18 22 22 ns t lz111ns t oh 1.5 1.5 1.5 ns t r c d 18 20 24 n s -6 -7 -8a symbol* min max min max min max units *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 45 16mb: x16 it sdram single write ? without auto precharge 1 timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s t wr 10 10 10 n s *cas latency indicated in parentheses. don ? t care disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqm / dqml, dqmh cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms active nop write nop precharge active t ah t as t ah t as single bank t ckh t cks column m 3 2 t0 t1 t2 t4 t3 t5 t6 nop -6 -7 -8a symbol* min max min max min max units note: 1. for this example, the burst length = 4, and the write burst is followed by a ? manual ? precharge. 2. 10ns is required between and the precharge command, regardless of frequency, to meet t wr. 3. a8, a9 = ? don ? t care. ?
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 46 16mb: x16 it sdram write ? without auto precharge 1 disable auto precharge bank 0 and 1 t ch t cl t ck t rp t ras t rcd t rc dqm 3 cke clk a0-a9 dq ba a10 t cmh t cms t cmh t cms t ah t as row row bank bank(s) bank row row bank t wr 4 don ? t care undefined d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command nop nop nop active nop write nop precharge active t ah t as t ah t as t dh t ds t dh t ds t dh t ds bank 0 or 1 column m (a0 - a7) 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s t wr 10 10 10 n s -6 -7 -8a symbol* min max min max min max units *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4, and the write burst is followed by ? manual ? precharge. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. 4. faster frequencies will require two clocks (when t wr > t ck).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 47 16mb: x16 it sdram write ? with auto precharge 1 enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm 3 cke clk a0-a9 dq ba a10 t cmh t cms t cmh t cms t ah t as row row bank bank row row bank t wr 4 don ? t care undefined d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command nop nop nop active nop write nop nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds column m (a0 - a7) 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s t wr 1 + 4ns 1 + 3ns 1 + 2ns t ck *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. 4. faster frequencies will require two clocks (when t wr > t ck). -6 -7 -8a symbol* min max min max min max units
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 48 16mb: x16 it sdram -6 -7 -8a symbol* min max min max min max units t ch t cl t ck clk dq don ? t care undefined d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command nop nop active nop write nop active t dh t ds t dh t ds t dh t ds active write t dh t ds d in b + 1 d in b + 2 t dh t ds t dh t ds enable auto precharge dqm 3 a0-a9 ba a10 t cmh t cms t cmh t cms t ah t as t ah t as t ah t as row column m (a0 - a7) 2 row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks column b (a0 - a7) 2 d in b t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 t wr - bank 0 4 t rcd - bank 1 t t rc - bank 0 rrd alternating bank write accesses 1 timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t ras 42 120,000 42 120,000 48 120,000 ns t rc 60 70 80 n s t r c d 18 20 24 n s t rp 18 21 24 n s t r r d 12 14 16 n s t wr 1 + 4ns 1 + 3ns 1 + 2ns t ck *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. 4. faster frequencies will require two clocks (when t wr > t ck).
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 49 16mb: x16 it sdram write ? full-page burst t ch t cl t ck t rcd dqm 2 cke clk a0-a9 ba a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed. 256 locations within same row. don ? t care undefined command nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t dh t ds column m (a0 - a7) 1 t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t cms t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 3 -6 -7 -8a symbol* min max min max min max units t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t r c d 18 20 24 n s timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns *cas latency indicated in parentheses. note: 1. a8 and a9 = ? don ? t care. ? 2. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte. 3. page left open; no t rp.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 50 16mb: x16 it sdram t ch t cl t ck t rcd dqm 3 cke clk a0-a9 dq ba a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh t cms t cmh command nop nop nop active nop write nop nop don ? t care undefined t dh t ds t dh t ds t ah t as t ah t as disable auto precharge column m (a0 - a7) 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 write ? dqm operation 1 -6 -7 -8a symbol* min max min max min max units t ckh 1 1 1 ns t cks 2 2 2 ns t cmh111ns t cms 2 2 2 ns t dh111ns t ds222ns t r c d 18 20 24 n s timing parameters -6 -7 -8a symbol* min max min max min max units t ah111ns t as222ns t ch 2.5 2.75 3 ns t cl 2.5 2.75 3 ns t ck (3) 6 7 8 ns t ck (2) 8 10 13 ns t ck (1) 20 25 25 ns *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4. 2. a8 and a9 = ? don ? t care. ? 3. dqm represents dqml and dqmh. dqml controls the lower byte, and dqmh controls the upper byte.
16mb: x16 it sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx16it.p65 ? rev. 5/99 ?1999, micron technology, inc. 51 16mb: x16 it sdram 50-pin plastic tsop (400 mil) c-4 0.10 10.21 10.11 0.45 0.30 0.80 typ 2.80 50 125 see detail a 1.2 max 0.25 detail a gage plane pin #1 id r 1.00 (2x) r 0.75 (2x) 0.25 0.05 0.18 0.13 21.04 20.88 11.86 11.66 0.80 typ 0.60 0.40 0.10 (2x) 0.88 note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.01" per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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